WARP-V Core Configurator

EXTRA_*_BUBBLEs (0 or 1). Set to 1 to add a cycle to the replay condition and relax circuit timing. (Not all configurations are valid.)

EXTRA_REPLAY_BUBBLE

EXTRA_PRED_TAKEN_BUBBLE

EXTRA_JUMP_BUBBLE

EXTRA_BRANCH_BUBBLE

EXTRA_INDIRECT_JUMP_BUBBLE

EXTRA_NON_PIPELINED_BUBBLE

EXTRA_TRAP_BUBBLE

Enable custom programInclude template for custom instructions

Here, you can provide your own assembly program that will be hardcoded into the instruction memory of your core. The syntax roughly mimics that defined by the RISC-V ISA, but not exactly.

# /=====================\
# | Count to 10 Program |
# \=====================/
#
# Default program for RV32I test
# Add 1,2,3,...,9 (in that order).
# Store incremental results in memory locations 0..9. (1, 3, 6, 10, ...)
#
# Regs:
# t0: cnt
# a2: ten
# a0: out
# t1: final value
# a1: expected result
# t2: store addr
reset:
   ORI t2, zero, 0          #     store_addr = 0
   ORI t0, zero, 1          #     cnt = 1
   ORI a2, zero, 10         #     ten = 10
   ORI a0, zero, 0          #     out = 0
loop:
   ADD a0, t0, a0           #  -> out += cnt
   SW a0, 0(t2)             #     store out at store_addr
   ADDI t0, t0, 1           #     cnt++
   ADDI t2, t2, 4           #     store_addr++
   BLT t0, a2, loop         #  ^- branch back if cnt < 10
# Result should be 0x2d.
   LW t1, -4(t2)            #     load the final value
   ADDI a1, zero, 0x2d      #     expected result (0x2d)
   BEQ t1, a1, pass         #     pass if as expected

# Branch to one of these to report pass/fail to the default testbench.
fail:
   ADD a1, a1, zero         #     nop fail
pass:
   ADD t1, t1, zero         #     nop pass

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